Display devices have employed cathode-ray tubes (CRT) to display images. However, various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, and electro-luminescent display (ELD) devices, are currently being developed as substitutes for the CRT. Among these various types of flat panel displays, LCD devices have advantages of thin profile and low power consumption, but have disadvantages of using a backlight unit because they are non-luminescent display devices. However, as organic electroluminescent display (OELD) devices are self-luminescent display devices, they are operated at low voltages and have a thin profile. Further, the OELD devices have advantages of fast response time, high brightness and wide viewing angles.
As illustrated in FIG. 1, a gate line GL is extended along a row line, and a data line DL is extended along a column line perpendicular to the row line, and the gate and data lines GL and GL define a pixel region P. In the pixel region P, first and second switching thin film transistors (TFT) T1 and T2, and first and second driving TFT T3 and T4 are formed. The first and second switching TFT T1 and T2 and the second driving TFT T4 use a PMOS TFT, and the first driving TFT T3 uses a NMOS TFT.
The first and second switching TFT T1 and T2 are connected in series. The source electrode of the first switching TFT T1 is connected to a first electrode of a storage capacitor Cst, and a drain electrode of the second switching TFT T2 is connected to the data line DL. A second electrode of the storage capacitor Cst is connected to a power supply line VDDL supplying a power voltage (VDD). The first and second driving TFT T3 and T4 are connected in series. A source electrode of the second driving TFT T4 is connected to the power supply line VDDL, and a gate electrode of the second driving TFT T4 is connected to the source electrode of the first switching TFT T1. A source electrode of the first driving TFT T3 is connected to a first electrode (anode) of an organic electroluminescent diode OED. The second electrode (cathode) of the OED is grounded.
Gate electrodes of the first and second switching TFT T1 and T2 and the first driving TFT T3 are connected to the gate line GL. The gate electrode of the second driving TFT T4 is connected to the source electrode of the first switching TFT T1.
FIG. 2A is a timing chart illustrating a gate signal and a current (ISIG) of an OELD device of FIG. 1. FIG. 2B is a circuit diagram illustrating a pixel region, to which an “on” gate signal is applied, of an OELD device of FIG. 1; and, FIG. 2C is a circuit diagram illustrating a pixel region, to which an “off” gate signal is applied, of an OELD device of FIG. 1.
When an “on” (negative) gate signal is applied to the gate line GL during a first period a of one frame period, the first and second switching TFT T1 and T2 are turned on and the first driving TFT T3 is turned off, as shown in FIG. 2B. Accordingly, the second driving TFT T4 is turned on, and thus a current (ISIG) flows from the power supply line VDD to the data line DL through the second driving TFT T4. At this time, a data signal (Vdata) from the data line DL is applied to the gate electrode of the second driving TFT T4, and thus the second driving TFT T4 has a gate voltage Vg=VDD−Vth+Vdata, where Vth is a threshold voltage. The gate voltage Vg is stored in the storage capacitor Cst. Since the first driving TFT T3 is turned off during the first period, a, a current does not flow in the organic electroluminescent diode OED.
When an “off” (positive) gate signal is applied to the gate line GL during a second period, b, of one frame period, the first and second switching TFT T1 and T2 are turned off and the first driving TFT T3 is turned on, as shown in FIG. 2C. Since the first driving TFT T3 is turned on during the second period, b, a current (Ioeld) flows on the organic electroluminescent diode OED. An amount of the current (Ioeld) flowing on the organic electroluminescent diode OED is determined according to an amplitude of the gate voltage Vg stored in the storage capacitor Cst, and in particular the data signal (Vdata). In other words, the current (Ioeld) is expressed as Ioeld=K(Vgs−|Vth|)2=K(VDD−Vth+Vdata−VDD−|Vth|)2=K(Vdata)2. The expression for current (Ioeld) flowing in the organic electroluminescent diode OED has no terms representing either the power voltage (VDD) and or the threshold voltage (Vth).
Therefore, the related art OELD device of FIG. 1 prevents degradation of display quality by compensation of the threshold voltage (Vth) and a drop of the power voltage (VDD). In addition, the related art OELD device of FIG. 1 increases the aperture ratio because it requires one gate line for one pixel. However, since the related art OELD device of FIG. 1 uses both PMOS and NMOS TFT on the same substrate, and the cost to fabricate both PMOS and NMOS TFT increases.
FIG. 3A is a circuit diagram of another type OELD device according to the related art, and FIG. 3B is a timing chart illustrating gate signals and a current (ISIG) of an OELD device of FIG. 3A.
As shown in FIGS. 3A and 3B, the related art OELD device has prior and post gate lines GL1 and GL2 in a pixel region P. A data line (not shown) crosses the prior and post gate lines GL1 and GL2 to define the pixel region P. In the pixel region P, first and second switching thin film transistors (TFT) T1 and T2, and first and second driving TFT T3 and T4 are formed.
The first and second switching TFTs T1 and T2 and the first and second driving TFT T3 and T4 use PMOS TFT. In other words, the OELD device of FIG. 3A has the PMOS TFT as the first driving TFT T1, differing from the OELD device of FIG. 1. The first and second switching TFT T1 and T2 are connected to the prior gate line GL1 and turned on or off according to a prior gate signal, and the first driving TFT T3 is connected to the post gate line GL2 and turned on or off according to a post gate signal.
When an “on” (negative) prior gate signal is applied to the prior gate line GL1 during a first period, a, of one frame period, the data signal (Vdata) is applied to the gate electrode of the second driving TFT T4 and a current (ISIG) flows from the power supply line VDDL to the data line. When the “on” (negative) prior gate signal of the prior gate line GL1 is finished, an “on” (negative) post gate signal starts to be applied to the post gate line GL2 and the first driving TFT T3 is turned on. The “on” post gate signal is applied during a second period b of one frame period. Accordingly, a current (Ioeld) flows in an organic electroluminescent diode (OED).
The OELD device of FIG. 3A has the same operational characteristics as the OELD device of FIG. 1, and in addition, it uses the PMOS TFT as the switching and driving TFT. Accordingly, fabrication cost is reduced.
As explained above, the data signal (Vdata) is applied to the gate electrode of the second driving TFT T4 during the first period, a, and the current (Ioeld) flows during the second period, b, thus a display image for one frame is displayed. In other words, the display image is displayed during the second period, b, i.e., a period subtracting the first period a from one frame period, and to do this, an on gate signal is applied to the post gate line GL2 during the second period, b. However, since the post gate line GL2 is applied with an “on” gate signal during a long interval of the second period, b, distortion of signals is caused and the distortion of signals causes degradation of display quality. In addition, to prevent these problems, a separate external drive IC supplying an on gate voltage to the post gate line GL2 is required.